The present invention is directed to gaseous discharge display apparatus of the type commonly known as a plasma display panel or AC plasma panel as described in U.S. Pat. No. 3,559,190. The plasma panel includes a pair of dielectric members with a respective array of panel electrodes isolated from a gaseous medium. By couplinq a suitable drive circuit to respective electrodes in the commonly configured row and column panel array, the associated intersecting display cell or "pixel" on the panel can be displayed. Reference may be made to the aforementioned U.S. patent in which there is indicated a variety of addressing techniques for entering information into the plasma panel as well as techniques for sustaining the displayed information in the panel after addressing.
The AC plasma display panel has been the most commercially successful flat panel display technology used for large computer terminal displays. It is second only to the cathode ray tube in the number of computer terminals sold. The most costly portion of presently available AC plasma display systems is the electronic drive circuits. For instance, a 512.times.512 AC plasma display panel (i.e., one having an array of 512 row panel electrodes and 512 column panel electrodes) requires 1024 panel electrode drive circuits. Although integrated circuits have significantly reduced the cost of these drivers, the circuit part of the display system is still the major part of the total system cost. The thousand or so drivers required for a plasma display is frequently compared to the approximately 10 drive circuits required by a cathode ray tube. Thus, circuit costs are a major reason for the cathode ray tube's cost advantage over plasma displays.
It is thus desired to drastically reduce the adressing or drive circuit costs for plasma panels without significantly increasing the plasma panel manufacturing costs.
One proposed solution is to make the plasma display panel behave as a shift register and thereby provide a "shift panel". Addressing speed is low because a discharge point or pixel on the panel is accessed only after the information is shifted through many other pixels. Large size panels cannot be made because the shift panel yield is low. Yields are low because every pixel in a shift panel must be good and reliably capable of display (i.e., without cell contamination or broken panel electrodes) or the rest of the information in the line will be lost. Display panels with missing lines are not commercially usable. Most shift panels will shift in only one dimension so that the savings in drive circuits influences only that dimension. For instance, a 512.times.512 shift panel could be accomplished by 512+3=515 circuit drivers which is about half of the 1024 required by a standard plasma panel. However, this circuit driver reduction may be offset by the increased cost of the plasma panel due to reduced yield of the more complicated shift panel. Thus, the shift technique is probably not the ultimate solution to the panel drive circuit problem.
Another proposed technique for reducing the number of drive circuits in a plasma display utilizes gas discharge logic. Reference may be made for instance to the following published articles: (1) "Discharge-Logic Drive Schemes", by J. D. Schermerhorn and J. W. V. Miller, IEEE Transactions On Electron Devices, Vol. ED - 22, No. 9, September 1975, pages 669-673; (2) "Coupled-Matrix, Threshold- Logic AC Plasma Display Panel", T. N. Criscimagna, J. R. Beidl, M. Steinmetz and J. Hevesi, Proceeding of the SID, Vol. 17/4, 4th Quarter 1976, pages 176-179.
In such proposed gas discharge logic addressing techniques, each discharge point or display pixel on the plasma panel is provided with two row (X) electrodes and two column (Y) electrodes. A particular pixel is selected for display only if suitable signals are provided on all four input electrodes, and thus the pixel can be considered a four input AND gate. The input panel electrodes for each pixel are grouped such that for a 512.times.512 panel only 48 circuit drivers for the row electrodes and 48 circuit drivers for the column electrodes, or a total of 96 circuit drivers are required. In the addressing configuration, each row and column axis may contain groups of 32 electrodes connected in parallel to one driver circuit and groups of 16 electrodes also connected in parallel to a single driver circuit.
Such a proposed technique has led to significant problems. First, the electrodes are grouped together and connected to conductor buses in a way that requires electrical crossovers in the panel. The crossovers must be of low capacitance and must withstand voltage breakdown due to the address pulses, which renders manufacturing of a suitable plasma panel significantly more complex. Another major problem is the significant increase in capacitance which the address circuits must drive compared to a conventional plasma panel. For example, in the case of a 512.times.512 panel, where 32 electrodes are connected in parallel and to one driver, the capacitive load on each driver circuit is increased by 32 times. In addition, the double electrode structure per pixel will increase the capacitance of each electrode as seen by the drivers. Thus, the capacitance viewed by an addressing or driver circuit for this technique can be as much as 100 times greater, for a 512.times.512 panel, as compared to a conventional panel.
Furthermore, since the capacitive load on each driver is increased by a factor of 32, the discharge current of each panel electrode will also increase by a factor of 32 utilizing this proposed technique. Increasing the drive current requirement by a factor of 32 requires a proportional increase in the output circuit silicon area of an integrated circuit driver, which may lead to obtaining considerably fewer output drivers and associated circuits on an integrated circuit chip. Thus, the reduction in the number of drive circuit connections to the plasma panel theoretically obtainable with this proposed technique may not significantly reduce the number of integrated circuit chips because of the resulting greatly decreased number of output circuits per chip. Since most of the cost of the integrated circuit is in the packaging, there also may be no significant cost advantage of this heretofore proposed gas discharge logic technique for addressing plasma panels as compared to a conventional plasma panel system because of the roughly equivalent number of integrated circuit chips required to drive each panel in the respective systems.
It is therefore desired to provide a gas discharge logic device which would be particularly adaptable for use in addressing AC plasma panels to reduce the number of panel eletrode drive circuits normally required for the panel and which would provide the following features: (1) Does not significantly increase the capacitive load and the current load of the output drivers over that of a conventional system so that existing integrated circuit drivers can be used; (2) Does not require electrical crossovers on the plasma panel so that the plasma panel need not be manufactured with electrical feedthroughs or other complicated and costly panel processing steps; (3) Ideally the new technique should require little more than a mask change for a new panel electrode pattern during panel construction, and a new set of panel electrode drive waveforms; (4) Any new panel electrode pattern should not require critical registration steps that significantly reduce the plasma panel yield.